1. Field of the Invention
The present invention relates to a latch circuit and a semiconductor device including the latch circuit. Note that the semiconductor device in this specification indicates any device that can operate by utilizing semiconductor characteristics.
2. Description of the Related Art
A latch circuit is a circuit that can temporarily hold a specific logic state (hereinafter also referred to as data), and is used in a variety of semiconductor devices. For example, a latch circuit is used as a circuit that temporarily hold data when the data is written or read to/from a storage circuit provided in a semiconductor device.
The latch circuit can be constituted by logic gates. For example, there are an SR latch circuit illustrated in FIG. 26A, an /SR latch circuit illustrated in FIG. 26C, a JK latch circuit illustrated in FIG. 26E, a gated SR latch circuit illustrated in FIG. 26G, and a D latch circuit illustrated in FIG. 26I. FIG. 26B shows the truth table of the SR latch circuit in FIG. 26A. FIG. 26D shows the truth table of the /SR latch circuit in FIG. 26C. FIG. 26F shows the truth table of the JK latch circuit in FIG. 26E. FIG. 26H shows the truth table of the gated SR latch circuit in FIG. 26G. FIG. 26J shows the truth table of the D latch circuit in FIG. 26I.
In the latch circuit constituted by logic gates as illustrated in FIGS. 26A to 26J, stored data is lost when power supply is stopped. In addition, a large number of semiconductor elements (such as transistors) are required to form the latch circuit.
Further, a latch circuit can be constituted by a non-volatile ferroelectric element (see Patent Document 1). In that case, data can be held in the ferroelectric element even when power supply is stopped. However, when the ferroelectric element is used, deterioration of data retention due to the increase in the number of rewrite operations tends to be obvious.